Senior Digital IC Verification Engineer

Main responsibilities
• Oversee the digital IC verification in assigned projects
• Construct, maintain, and improve verification platforms of SoC and building blocks
• Hands-on digital IC verification, including but not limited to build and reuse models,
monitors, and checkers; debug failures and manage bug tracking; collect, analyze,
and improve function coverage and code coverage
• Specify verification requirements, procedures, use cases; instruct reports writing
• Improve the verification methodology, try to reduce the verification time while
maintaining high validation quality
Minimum Qualification
• At least bachelor degree related to electronics
• Preferably >6~10 years of experience in digital IC verification
• Expertise in all digital IC verification steps (RTL, gate level, formal verification)
• Proficiency in hardware languages like Verilog, SystemVerilog
• Deep knowledge in UVM methodology, and experiences in building verification
platforms

Hero Meets Hero!
• Familiar with digital IC design process and skilled in simulation tools for debugging, like VCS, Modelsim
• Experiences in hardware/software co-simulation and mixed-signal verification
• Basic knowledge in deep neural networks
Additionally, we look for the following universal qualities in all candidates:
• Resourceful Achiever: self-driven and proactive. You apply logic and reason to solve problems effectively and manage risks.
• Avid Learner: you eagerly take on new challenges and seek out opportunities to grow and stretch.
• Passionate Owner: you are energized by your work, taking ownership, and delivering results without ego.
• Committed Collaborator: with a positive attitude and commitment to get to the best result, you welcome ideas from others and drive processes forward in an inclusive manner
• Work location
Zürich, Switzerland