RTL Engineer
(6+ years exp)$2k – $3k
Published: 1 month ago
ViShare Technology
Video codec chip for low-latency wireless video streaming and HDMI over IP
Job Location
Job Type
Full TimeVisa Sponsorship
Not AvailableHires remotely
Everywhere
Relocation
AllowedSkills
Verilog
FPGA
SystemVerilog
System Verilog
ASIC and FPGA Design
VHDL / Verilog
Hiring contact
Alina IvanovaThe Role
Company:
ViShare Technology Limited is a venture-backed fabless semiconductor company focusing on developing low-latency wireless video transmission technology headquartered in Hong Kong. ViShare’s technology offers the lowest latency and most stable WiFi-based HD/4K video transmission solution providing the visual lossless experience indistinguishable from HDMI cables. The technology can be widely applied to wireless AR/VR, drone FPV(First Person View), gaming, etc.
Responsibilities:
- Perform architectural design
- Perform RTL coding, verification, and optimization
- System-level verification using software and FPGA prototype board.
- Interface with back-end ASIC design team for physical implementation.
- Prepare technical documentation
Requirements:
- Bachelor or above in Electronic Engineering or equivalent. The higher degree would be considered as an advantage.
- Good experience of FPGA/ASIC design
- Good experience of VHDL/Verilog; SystemVerilog is a plus
- Knowledge of scripting languages such as Perl, TCL, and Makefile is preferable.
- Good skill in communication, teamwork, and problem solving
- Good English is preferable
ViShare Technology Limited is a venture-backed fabless semiconductor company focusing on developing low-latency wireless video transmission technology headquartered in Hong Kong. ViShare’s technology offers the lowest latency and most stable WiFi-based HD/4K video transmission solution providing the visual lossless experience indistinguishable from HDMI cables. The technology can be widely applied to wireless AR/VR, drone FPV(First Person View), gaming, etc.
Responsibilities:
- Perform architectural design
- Perform RTL coding, verification, and optimization
- System-level verification using software and FPGA prototype board.
- Interface with back-end ASIC design team for physical implementation.
- Prepare technical documentation
Requirements:
- Bachelor or above in Electronic Engineering or equivalent. The higher degree would be considered as an advantage.
- Good experience of FPGA/ASIC design
- Good experience of VHDL/Verilog; SystemVerilog is a plus
- Knowledge of scripting languages such as Perl, TCL, and Makefile is preferable.
- Good skill in communication, teamwork, and problem solving
- Good English is preferable
Similar Jobs
viAct
AI save lives - we believe worker lives matter
Ambi Labs
The Smart Add-On For Your AC
RC Labs
Intelligent Battery Management Systems
Gritus Technology
Smart City. Smart Vending
TR at CUHK Company
Foster collaboration and catalyse innovation
TR at CUHK Company
Foster collaboration and catalyse innovation
TR at CUHK Company
Foster collaboration and catalyse innovation
Galxe
The largest Web3 credential data network in the world