Designed an ISA and micro engine for a statically scheduled MIMD system (56k processors).
Designed a routing network and microcode for an MIMD computer with 14*64*64 processors. patented.
Designed a new complex language, supervised a team of 25 that built the compiler (300k lines of heavy duty C++) and tool for front end chip design (don't build tools that require a methodology/architectural sale).
Designed a new look up engine for internet routing. Patent pending.
Part of the Intel Pentium Pro (P6) reservation station. Scheduling circuits which used precharge and domino logic (VLSI) to select the next micro ops to execute.