Responsible for multiple designs of Content Addressable SRAM Memory. Developed a memory compiler to facilitate automated design of memory flavors. ·… · More 12 SPARC S3 cores with 96 threads, 48MB L3 cache, 1TB maximum memory per socket with upto 4.27 billion transistors and 4.1 Tbps bandwidth.
Project focused on the design of an energy efficient on-chip DC-DC converter and an ultra-low power rectifier circuit. The aim was to negate the need of… · More off-chip DC-DC converters and extract power from various energy harvesters to drive various low-power portable devices.